Job
- Level
- Experienced
- Job Field
- Embedded, Test/QA
- Employment Type
- Full Time
- Contract Type
- Permanent employment
- Location
- Villach
- Working Model
- Onsite
Job Summary
In this role, you will create verification plans for mixed-signal designs and develop test environments in SystemVerilog using UVM. You will execute tests at RTL and gate-level while collaborating closely with designers.
Job Technologies
Your role in the team
- Create and define verification plans for digital verification of Mixed Signal designs.
- Create new and improve existing verification environments in SystemVerilog language using Universal Verification Methodology (UVM) and Constrained Random approach.
- Execute tests in these environments on RTL and gate-level and debug issues in design and verification environments.
- Closely cooperate with analog and digital designers as well as concept and other verification engineers.
- Mentoring of junior colleagues, consultants, and students.
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Our expectations of you
Education
- A university degree in Electrical Engineering, Computer Science, Information Technology, or a similar academic discipline.
Qualifications
- You work conscientiously on making things better, faster, and more efficient and keep up high quality standards for yourself and other people.
- You can solve technical problems and work independently.
- You are a team player and support your colleagues for the overall team and company success.
- Excellent know-how with UVM, especially using SystemVerilog.
- Knowledge of RTL design (HDL) and digital or analog circuits.
- Knowledge of Cadence verification software (Xcelium and vManager) or similar.
- Knowledge of GIT, Python, and other programming languages is a plus.
- Fluency in English.
Experience
- Ideally 3-5 years of related work experience.
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Benefits
More net
- 💻Company Notebook for Private Use
- 💰Bonus Commisions
- 💵Bonus Payments
- 👴🏻Company Retirement Provision
- 👷♂️Additional Insurance
Health, Fitness & Fun
Work-Life-Integration
Food & Drink
Job Locations
Location Villach
Kärnten
Austria
Topics that you deal with on the job
This is your employer
Infineon Technologies Austria AG
Villach, Klagenfurt, Graz, Linz
Infineon Technologies Austria AG, with its headquarters in Villach, is a subsidiary of Infineon Technologies AG. Besides Germany, Austria is the only location where Infineon combines the skills for research and development, manufacturing and global business responsibility.
Description
- Language
- English
- Company Type
- Established Company
- Working Model
- Full Remote, Hybrid, Onsite
- Industry
- Industry, Production, Electronics, Automatization
Dev Reviews
by devworkplaces.com
Total
(3 Reviews)3.0
Engineering
2.9Culture
2.5Workingconditions
4.2Career Growth
2.6
Staff Engineer Functional Digital Verification
- Location
- Villach
- Working Model
- Onsite
