VHDL Job in Villach

Creation and maintenance of verification plans Verification plan execution, tracking and documentation Choosing the right verification methodology Defining verification metrics Setting up verification environments Executing tests in these environments...

As our new Mixed Signal Test Engineer (f/m/div)* you work in a highly professional team being responsible for the definition of test concepts and test cases in close cooperation with concept engineers, design engineers and lab verification engineers....

Be responsible for digital design (System Verilog / VHDL coding), verification, simulation, synthesis and static timing analysis Define digital algorithms and architecture Implement design for test concepts Closely cooperate with analogue and digital...

Be responsible for digital design (System Verilog / VHDL coding), verification and simulation Implement design for test concepts Closely cooperate with analogue and digital designers and verification engineers Support hardware post-silicon validation in...

Support R&D chip designer and verification engineers for daily issues related to mixed-signal IC development flow and related software tools and methodology (1st level support) Proactively consult chip design projects to ensure proper and efficient...